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copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. high-performance, high-current drmos power module apw8706a features general description 4.5v ~ 5.5v input range for vcc & pvcc 4.5v ~ 25v input range for vin power-on-reset monitoring on vcc pin up to 8a (peak), 6a (continuous) output current scale adjustable over-current protection threshold up to 1.5mhz pwm operation built-in tri-state pwm input function built in en timing control function build in n-ch mosfet for high side, n-ch mosfet for low side skip mode operation over-temperature protection tqfn 4x4-23 package lead free and green devices available (rohs compliant) desktops graphics cards severs portable/notebook regulators the apw8706a integrates a high-side n-channel mosfet and a low-side n-channel mosfet with adap- tive dead-time control. the apw8706a have a built-in tri- state pwm input function which can support a number of pwm controllers. when the pwm input signal stays tri- state, the tri-state function shuts off the high-side mosfet and turns on the low-side mosfet without consider zc function. the device is also equipped with power-on- reset(por) and enable control functions into a single package and accurate current limit. the device over-cur- rent protection monitors the output current by using the voltage drop across the r ds(on) of low-side mosfet, elimi- nating the need for a current sensing resistor that fea- tures high efficiency and low cost. the por circuit with hysteresis monitors vcc supply voltage to start up/shut- down the ic at power-on/off. the apw8706a also can be enabled or disabled by other power system. pulling the en pin high or low will turn on or shut off the device. simplified application circuit applications c in vin agnd pwm vcc pgnd lx en v cc v out v in c vcc 1uf c out l pwm controller vcc pvcc apw8706a
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 2 apw8706a ordering and marking information pin configuration note:anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j-std-020d for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). = exposed and thermal pad tqfn 4x4-23 (top view) lx agnd5 pwm6 ocset1 ocb2 en3 smod4 n c 7 8 9 1 0 l x 1 1 17lx 16lx 15 14pgnd 13pgnd 12 pgnd 2 3 2 2 v c c 2 1 2 0 1 9 b s t 1 8 l x vin v i n p v c c l x v i n v i n p g n d pgnd 24 25 apw8706a handling code temperature range package code assembly material apw8706aqb: package code qb : tqfn 4x4-23 operating ambient temperature range handling code tr : tape & reel assembly material g : halogen and lead free device x - date code i : -40 to 85 o c a apw8706 xxxxx
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 3 apw8706a absolute maximum ratings (note 1) symbol parameter rating unit v cc & v pvcc vcc & pvcc to gnd voltage -0.3 ~ 7 v v in vin to pgnd voltage -0.3 ~ 30 v v lx lx to pgnd voltage >20ns pulse width <20ns pulse width -0.3 ~ 30 -5 ~ 38 v v bst bst to gnd voltage -0.3 ~ 37 v v bst -v lx bst to lx voltage -0.3 ~ 7 v other pins en,smod, ocset and pwm to agnd voltage -0.3 ~ v cc +0.3 v agnd to pgnd voltage -0.3 ~0.3 v t j junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature(10 seconds) 300 o c note1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recom- mended operating conditions is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) tqfn4x4-23 50 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. symbol parameter range unit v cc &v pvcc vcc and pvcc to agnd voltage 4.5 ~ 5.5 v v in vin to pgnd voltage 4.5 ~ 25 v maximum continuous output current 6 a i out maximum peak output current 8 a f pwm pwm operation frequency 0.1 ~ 1.5 mhz t pwm_off pwm input minimum off time 200 ~ ns t a ambient temperature -40 ~ 85 o c t j junction temperature -40 ~ 125 o c recommended operating conditions (note 3) note 3: refer to the typical application circuit.
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 4 apw8706a electrical characteristics apw8706a symbol parameter test conditions min. typ. max. unit supply current en = high, pwm = high, smod=l - 90 120 ua en = high, pwm = low, smod=l - 90 120 ua i vcc vcc supply current en = low - - 1.0 ua power-on-reset(por) vcc rising por thresold 3.7 4.0 4.3 v vcc por hysteresis - 120 - mv bootstrap r bst bst switch on resistance bst source 10ma - 33 - bst leakage current v boot-pgnd =30v, v lx =25v - - 1 ua power stage r on_h high-side switch on resistance - 30 - m r on_l low-side switch on resistance - 12 - m high side mosfet leakage current v in =25v, v en = v lx =gnd -1 - 1 ua low side mosfet leakage current v in =v lx =v bst =25v, v en =gnd -1 - 1 ua zero current detect v zc zero current detect v lx - pgnd -5 - 5 mv over-current protection(ocp) i ocset ocset current source 9 10 11 a v ocp ocp threshold - 190 - mv ocb output low voltage sink current=5ma - 0.5 0.7 v ocb leakage current v ocb =5v - - 1 ua t d(ocb) ocb deglitch time ocb go low - 0.6 - ms over-temperature protection (otp) t otp otp rising threshold - 145 - o c otp hysteresis - 45 - o c pwm input pin v pwm rising 3.6 3.9 4.2 v v pwm_h pwm logic high threshold hysteresis - 150 - mv v pwm rising 1.2 1.5 1.8 v v tri_h tri-state input rising logic threshold hysteresis 300 400 550 mv v pwm falling 2.8 3.1 3.4 v v tri_l tri-state input falling logic threshold hysteresis 300 400 500 mv i pwm pwm pin input current source/ sink , v pwm = 0v to 5v -1 - 1 ua unless otherwise specified, these specifications apply over v cc = v pvcc = v en = 5v, v in =12v and t a = 25 o c.
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 5 apw8706a electrical characteristics (cont.) apw8706a symbol parameter test conditions min. typ. max. unit en input and smod input en input logic high 1.2 - - v en input logic low - - 0.4 v en input current v en = 5v -1 - 1 ua smod input logic high 1.5 - - v smod input logic low - - 0.4 v smod input current v smod =5v -1 - 1 ua gate driver timings(refer to figure 1 and table 1) t pdlu pwm to high side gate pwm h to l to gh h to l (note4) - 18 - ns t pdll pwm to low side gate pwm l to h to gl h to l (note4) - 25 - ns t pdhu ls to hs gate deadtime gl h to l to gh l to h (note4) - 20 - ns t pdhl hs to ls gate deadtime gh h to l to gl l to h (note4) - 20 - ns t trqu quit tri-state delay tri-state gl h to l to pwm h (note 4) - 40 - ns t tren enter tri-state delay gh h to l to tri-state gl l (note 4) - 120 - ns note4: not tested in production. unless otherwise specified, these specifications apply over v cc = v pvcc = v en = 5v, v in =12v and t a = 25 o c.
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 6 apw8706a pwm operation characteristics figure 1 : timing chart table 1 : truth table en smod pwm gh gl l x x l l h l h h l h l l l skip mode h x tri-state l l h h h h l h h l l h pwm gl t pdll gh tri-state band lx t pdhu t pdlu t pdhl t tr_en t tr_qu t tr_qu t tr_en
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 7 apw8706a pin descriptions pin number name function 1 ocset over-current setting input. connect a resistor to gnd to set the ocp trip level. 2 ocb fault indication pin. this pin goes low when a ocp condition is detected after a 0.6ms deglitch time. 3 en enable pin. logic high enables the device. logic low disables the device. the pin is not floating. 4 smod skip mode or pwm mode selection. ic enter skip mode when smod pull low; ic enter pwm mode when smod pull high. 5 agnd signal ground for the ic. all voltage levels are measured with respect to this pin. tie this pin to the ground island/plane through the lowest impedance connection available. 6 pwm pwm drive logic input. 7 nc no connection. 8,9,22,24 vin supply voltage input pin for power stage. 10,11,16,17,18,25 lx junction point of the high-side and low-side mosfet. connect the output lc filter for pwm output voltage. 12,13,14,15,19 pgnd power ground. 20 bst high-side gate driver power input pin. connect a 0.1uf capacitor from bst to lx. 21 pvcc supply voltage input pin for low side gate driver. 23 vcc supply voltage input pin for control circuitry. decoupling at least 1uf of a mlcc capacitor from the vcc pin to the agnd pin.
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 8 apw8706a operating waveforms enable ch1: v en , 5v/div ch2: v lx , 5v/div ch3: v pwm , 5v/div time: 10us/div 1 2 3 v en v lx v pwm shutdown ch1: v en , 5v/div ch2: v lx , 5v/div ch3: v pwm , 5v/div time: 10us/div 1 2 3 v en v lx v pwm 1 2 3 v lx v pwm v cc ch1: v pwm , 5v/div ch2: v lx , 5v/div ch3: v cc , 2v/div time: 1ms/div vcc power on 1 2 3 v ocb v lx v pwm v bst 4 ch1: v ocb , 5v/div ch2: v lx , 5v/div ch3: v bst , 5v/div ch4: v pwm , 5v/div time: 100us/div thermal shutdown
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 9 apw8706a operating waveforms (cont.) 1 2 3 4 ch1: v ocb , 5v/div ch2: v lx , 5v/div ch3: v bst , 5v/div ch4: v pwm , 5v/div time: 4us/div thermal shutdown release v ocb v lx v pwm v bst pwm operation v lx v pwm ch1: v lx , 5v/div ch2: v pwm , 2v/div time: 80ns/div 1 2 over current protection ch2: i l , 5a/div, dc ch3: v ocb , 5v/div, dc time: 500 m s/div ch1: v lx , 10v/div, dc 1 2 3 v lx i l v ocb r ocset =10k w
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 10 apw8706a block diagram power-on reset tri -state input circuit controller shoot through control pvcc vin lx pgnd vcc vcc en pwm agnd zero crossing detect lx gh gl gh gl bst smod ocb ocset 10ua + - + 190mv lx ocp pvcc +
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 11 apw8706a typical application circuit note 5: vcc voltage rail must be sync with pwm controller vcc voltage level. c in vin agnd pwm vcc pgnd lx en v cc(note5) v out v in c vcc 1uf c out l pwm controller vcc smod bst ocb 0.1uf pvcc r ocb 50k ocset r ocset c bst apw8706a
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 12 apw8706a function description vcc power-on-reset (por) a power-on-reset (por) function is designed to pre- vent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply voltage on the vcc pin if at least one of the enable pins is set high. when the vcc supply voltage exceeds the rising por threshold, the por enables the device. the por circuit has a hysteresis and a deglitch feature so that it will typically ignore undershoot transients on the vcc pin. smod apw8706a can be operated in the skip mode using smod pin. when smod is low, the ic will enter the skip mode. in skip mode if the pwm is low and the zc is detected, the gl will be pulled low, and low-side mosfet will be off. it is useful if the converter has to operation in skip mode to improve efficiency at light load. when smod is high, the converter will operate in force pwm mode. enable control pulling the ven above 1.2v will enable the driver output, and pulling ven below 0.4v will disable the driver output. if enable function is not used, connect en to vcc for normal operation. over-current protection (ocp) the over-current protection function protects the switch- ing converter to against over-current or short-circuit conditions. the ic senses the inductor current by detect- ing the drain to source voltage of low-side mosfet dur- ing it s on-state. when the inductor current is over the internal ocp trip point, the both of gate drivers will be latched off. figure 2. current limit algorithm pwm control the pwm pin has three states. if the pin is gave high level state, the internal pre-driver output of high-side (gh) goes high and internal pre-driver output of low-side (gl) goes low. if the pin is gave low level state, the gh goes low and gl goes high. if the pin is gave tri-state level, both gh and gl will go low. please refer to table 1. the current limit circuit employs a "peak" current-sens- ing algorithm (see figure 2). the apw8706a use the low- side mosfet s r ds(on) of the synchronous rectifier as a current-sensing element. if the magnitude of the current- sense signal at lx pin is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the current-limit threshold is given by: i limit =(190mv-r ocset *10ua)/r on_l time i n d u c t o r c u r r e n t 0 i limit i out i ocb output the apw8706a provide an open-drain output to indicate that a fault has occurred. when current-limit occurs for a deglitch time of t d(ocb) , the ocb goes low. since the ocb pin is an open-drain output, connecting a resistor to a pull high voltage is necessary. over-temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature t otr , the ic will enter the over temperature protection state that suspends the pwm, which forces the ug and lg gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 45 o c. the otp designed with a 45 o c hysteresis lowers the average t j during con- tinuous thermal overload conditions, which increases life- time of the apw8706a.
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 13 apw8706a layout consideration for all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. if the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. the input capacitors should be placed close to the vin pin, and the ground terminals of input capacitors and output capacitors should be close pgnd pin. 2. to minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the lx pin to minimize the noise coupling into other circuits. 3. the traces of pwm signal from the pwm controller to the pwm pin of apw8706a should be short to eliminate the parasitical capacitance; the parasitical capacitance will cause an invalid pwm signal.
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 14 apw8706a application information recommended minimum footprint 0.5 0.3 0.4 4mm * just recommend tqfn4x4-23 0.2 * 4mm thermalvia diameter 0.3mm x 12 2 . 7 - 1.35 0.4 0.25 0.95 0.25 0.25 2 . 9 5 0.25 0.5 unit:mm 0.2 0.05 0.13 0.02
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 15 apw8706a package information tqfn4x4-23 note : 1. follow from jedec mo-229 wccd-3. e d pin 1 b a a1 a3 nx aaa c e 1 pin 1 corner d1 d2 e 2 k l e 0.124 d2 2.95 3.15 0.116 0.057 e1 1.24 1.44 0.049 0.70 0.041 0.028 0.002 0.50 bsc 0.020 bsc k 0.20 0.008 3.90 4.10 0.154 0.161 3.90 4.10 0.154 0.161 0.08 aaa 0.003 s y m b o l min. max. 0.80 0.00 0.20 0.30 2.58 2.78 0.05 0.85 a a1 b d d1 e e2 e l millimeters a3 0.20 ref tqfn4x4-23 0.35 0.45 1.05 0.008 ref min. max. inches 0.032 0.000 0.008 0.012 0.102 0.109 0.033 0.014 0.018
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 16 apw8706a devices per unit carrier tape & reel dimensions package type unit quantity tqfn4x4 tape & reel 3000 application a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.50 0.10 p0 p1 p2 d0 d1 t a0 b0 k0 tqfn4x4 4.00 0.10 8.00 0.10 2.00 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 4.30 0.20 4.30 0.20 1.00 0.20 (mm) h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 17 apw8706a taping direction information tqfn4x4-23 user direction of feed classification profile
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 18 apw8706a classification reflow profiles profile feature sn-pb eutectic assembly pb-free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) (t s ) 100 c 150 c 60-120 seconds 150 c 200 c 60-120 seconds average ramp-up rate (t smax to t p ) 3 c/second max. 3 c/second max. liquidous temperature (t l ) time at liquidous (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak package body temperature (t p )* see classification temp in table 1 see classification temp in table 2 time (t p )** within 5 c of the specified classification temperature (t c ) 20** seconds 30** seconds average ramp-down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb-free process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm C 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process C classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 220 c 3 2.5 mm 220 c 220 c test item method description solderability jesd-22, b102 5 sec, 245 c holt jesd-22, a108 1000 hrs, bias @ 125 c pct jesd-22, a102 168 hrs, 100 % rh, 2atm, 121 c tct jesd-22, a104 500 cycles, -65 c~150 c hbm mil-std-883-3015.7 vhbm R 2kv mm jesd-22, a115 vmm R 200v latch-up jesd 78 10ms, 1 tr R 100ma reliability test program
copyright ? anpec electronics corp. rev. a.2 - feb., 2018 www.anpec.com.tw 19 apw8706a customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838

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